To expedite the development of mask sets for fabricating integrated circuits (ICs), chip designers typically combine standard cells from cell libraries. Cells may contain geometrical objects such as polygons (boundaries), paths, and other cells. Objects in the cell are assigned to “layers” of the design. Typically, the cell definitions are provided by a cell library vendor. The cell library vendor develops each cell separately with the expectation that IC layouts designed using the cell will meet specifications. For example, the Taiwan Semiconductor Manufacturing Company, Ltd. of Taipei, Taiwan, provides a GDSII cell library of over 550 standard cells for 0.13 micron technology.
The IC designer selects the cells it wishes to use in an IC layout to provide whatever structures are required for a particular application. Each cell has one or more connectivity targets, which are predetermined points used to connect the patterns in a pair of cells. The designer submits the configuration of cells to a routing program, which connects the target-containing patterns of the adjacent cells to form complete sets of patterns for each mask layer.
When a design incorporates two cells adjacent to each other in an IC layout, the router identifies the location of the connectivity target in each cell, and constructs a grid of regularly spaced points, such that each target coincides with a grid point. The router then constructs a connecting path between the targets, comprising one or more line segments that connect points of the grid. This connecting path is incorporated into the IC layout, so that the mask constructed from the connected cells includes continuous circuit paths.
In some cases, the connecting path constructed by the router overlaps (at least partially overlies and extends beyond) a circuit path in one or both cells. This occurs when the connectivity target in the cell is not located at the center of the circuit path connected to the feature containing the target. In that case, the masks formed from the circuit design include a merged line formed by the combined projection of the circuit path of the individual cell plus the connecting path formed by the router. The router merges the circuit path and the connecting path into a single line. The width of this merged projection may be greater than the nominal width for the technology used in the IC. For example, in a 0.13 micron IC, the combination of the circuit path and the connecting path formed by the router may result in the mask containing a line up to 0.25 micron wide.
The merged line (circuit path plus the overlapping connecting path) may be sufficiently thick (e.g., 0.25 micron) to require a greater distance between adjacent lines than the minimum required for the thinner line width of the original circuit path, based on the minimum spacing rule in effect for each line thickness. Because the router does not move the existing circuit paths when it constructs the connecting path, the increase in line thickness may even result in a small reduction in the distance between the merged line (formed by the circuit path and the connecting path) and the nearest adjacent line, at the same time that an increase is actually required.
Subsequently, when the IC layout is submitted for verification (for example, using a program such as Calibre, by Mentor Graphics of Wilsonville, Oreg.), the line spacing between each pair of adjacent lines is compared to the relevant minimum for that line. If the line spacing is less than the minimum required for the width of the merged line, a “wide wire” violation is identified. The existing cell designs are not usable for the desired layout.
The designer has two choices: (1) He or she can design a new IC layout; or (2) to render the current IC layout usable, the designer must ask the cell library vendor to revise the cell definition to increase the relevant line spacing, so that no “wide wire” violation occurs when the connecting path is added. Regardless of whether the designer adopts a different IC layout or waits for the cell library vendor to change the cell design, the cost and schedule for completing the IC project are likely to be adversely impacted.